module memory_to_buffer_test
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=6)
(
	input clk, wen, reset, en, release_data,
	input [ADDR_WIDTH-1:0] addr,
	input [7:0] baddr,
	input [DATA_WIDTH-1:0] data,
	output [DATA_WIDTH-1:0] reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7, reg_8	
);

	wire [DATA_WIDTH-1:0] mem_data;
	
	single_port_ram_memory 
	#(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram_mem(
		.clk(clk),
		.we(wen),
		.data(data),
		.addr(addr),
		.q(mem_data)
	);
	
	idct_buffer 
	#(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(8)) buffer(
		.clk(clk),
		.reset(reset),
		.release_data(release_data),
		.en(en),
		.data(mem_data),
		.addr(baddr),
		.reg_1(reg_1),
		.reg_2(reg_2),
		.reg_3(reg_3),
		.reg_4(reg_4),
		.reg_5(reg_5),
		.reg_6(reg_6),
		.reg_7(reg_7),
		.reg_8(reg_8)
	);
endmodule
